disable();
    oldinterrupt = getvect( com_port_hardware_interrupt_vector + 8 );
    setvect( com_port_hardware_interrupt_vector + 8, &newinterrupt );
    enable();

#define com_port_hardware_interrupt_vector 4
#define com_port_hardware_number 0x3f8
    com_port_hardware_interrupt_mask = inp( 0x21 ) & ( 1 << com_port_hardware_interrupt_vector );
    outp( 0x21, inp( 0x21 ) & ~( 1 << com_port_hardware_interrupt_vector ) );

#define com_port_receiving_register ( com_port_hardware_number + 0 )
#define com_port_interrupt_control_register ( com_port_hardware_number + 1 )
#define com_port_interrupt_identification_register ( com_port_hardware_number + 2 )
#define com_port_line_control_register ( com_port_hardware_number + 3 )
#define com_port_modem_control_register ( com_port_hardware_number + 4 )
#define com_port_line_status_register ( com_port_hardware_number + 5 )
#define com_port_modem_status_register ( com_port_hardware_number + 6 )

    com_port_line_control_mask = inp( com_port_line_control_register );
    com_port_interrupt_control_mask = inp( com_port_interrupt_control_register );
    com_port_modem_control_mask = inp( com_port_modem_control_register );
    outp( com_port_line_control_register, 0x80 );
    outp( com_port_receiving_register, 0x01 );
    outp( com_port_interrupt_control_register, 0x00 );
    outp( com_port_line_control_register, 0x03 );
    outp( com_port_interrupt_control_register, 0x0f );
    outp( com_port_modem_control_register, 0x0f );
    com_port_modem_status_mask = inp( com_port_modem_status_register );

    com_port_interrupt_identification_mask = inp( com_port_interrupt_identification_register );
    if( com_port_interrupt_identification_mask & 1 )
        _chain_intr( oldinterrupt );
    switch( ( com_port_interrupt_identification_mask >> 1 ) & 3 ){
        case 0:
            time0 = ticks() / freq;
            com_port_modem_status_mask = inp( com_port_modem_status_register );
            break;
        case 1:
//            outp( com_port_receiving_register, 0 );
            break;
        case 2:
            inp( com_port_receiving_register );
            break;
        case 3:
            inp( com_port_line_status_register );
            break;
        default:
            break;
    }
    outp( 0x20, 0x20 );

>     com_port_interrupt_identification_mask = inp(
> com_port_interrupt_identification_register );
>     if( com_port_interrupt_identification_mask & 1 )
> 	_chain_intr( oldinterrupt );
>     switch( ( com_port_interrupt_identification_mask
> >> 1 ) & 3 ){
> 	case 0:
> 	    time0 = ticks() / freq;
> 	    com_port_modem_status_mask = inp(
> com_port_modem_status_register );
> 	    break;
> 	case 1:
> //	      outp( com_port_receiving_register, 0 );
> 	    break;
> 	case 2:
> 	    inp( com_port_receiving_register );
> 	    break;
> 	case 3:
> 	    inp( com_port_line_status_register );
> 	    break;
> 	default:
> 	    break;
>     }
>     outp( 0x20, 0x20 );
> 

while (!(com_port_interrupt_identification_mask & 1)) {
// Здесь идет switch обработчика и выставляется флаг, что было обработано прерывание от порта
}
// Если флаг не установлен - передать по цепочке

#define SERIAL_IIR_FIFOS_ENABLED 0xc0

        DISABLE_ALL_INTERRUPTS(Extension->Controller);

	WRITE_MODEM_CONTROL(
		Extension->Controller,
		(UCHAR)SERIAL_MCR_OUT2
		);

        //
        // See if this is a 16550.  We do this by writing to
        // what would be the fifo control register with a bit
        // pattern that tells the device to enable fifo's.
        // We then read the iterrupt Id register to see if the
        // bit pattern is present that identifies the 16550.
        //

        WRITE_FIFO_CONTROL(
            Extension->Controller,
            SERIAL_FCR_ENABLE
            );

        regContents = READ_INTERRUPT_ID_REG(Extension->Controller);

        if (regContents & SERIAL_IIR_FIFOS_ENABLED) {
// ФИФО присутствует, это 16550(А)
        }

// Offsets from the base register address of the
// various registers for the 8250 family of UARTS.
//
#define RECEIVE_BUFFER_REGISTER    ((ULONG)((0x00)*SERIAL_REGISTER_STRIDE))
#define TRANSMIT_HOLDING_REGISTER  ((ULONG)((0x00)*SERIAL_REGISTER_STRIDE))
#define INTERRUPT_ENABLE_REGISTER  ((ULONG)((0x01)*SERIAL_REGISTER_STRIDE))
#define INTERRUPT_IDENT_REGISTER   ((ULONG)((0x02)*SERIAL_REGISTER_STRIDE))
#define FIFO_CONTROL_REGISTER      ((ULONG)((0x02)*SERIAL_REGISTER_STRIDE))
#define LINE_CONTROL_REGISTER      ((ULONG)((0x03)*SERIAL_REGISTER_STRIDE))
#define MODEM_CONTROL_REGISTER     ((ULONG)((0x04)*SERIAL_REGISTER_STRIDE))
#define LINE_STATUS_REGISTER       ((ULONG)((0x05)*SERIAL_REGISTER_STRIDE))
#define MODEM_STATUS_REGISTER      ((ULONG)((0x06)*SERIAL_REGISTER_STRIDE))
#define DIVISOR_LATCH_LSB          ((ULONG)((0x00)*SERIAL_REGISTER_STRIDE))
#define DIVISOR_LATCH_MSB          ((ULONG)((0x01)*SERIAL_REGISTER_STRIDE))
#define SERIAL_REGISTER_SPAN       ((ULONG)(7*SERIAL_REGISTER_STRIDE))